1. Field of the Invention
The present invention relates to semiconductor memory devices ensuring high-speed access therefor.
This application claims priority on Japanese Patent Application No. 2007-168947, the content of which is incorporated herein by reference.
2. Description of the Related Art
In conventionally-known semiconductor memory devices, multiple bonding pads (simply referred to as pads) are formed in the peripheries of regions forming memory cells in chips. Pads are connected to terminals of packages of semiconductor memory devices via bonding wires, thus performing transmission and reception of signals with external devices.
In order to achieve high-speed access of memory cells, memory cell arrays are divided into multiple banks, thus increasing the speed for reading and writing data with memory cells.
The aforementioned structure may increase access speed in reading and writing data with individual memory cells; however, it increases wire drawing lengths with respect to wires connecting between banks and pads in the peripheries. That is, it becomes difficult to further increase access speeds above prescribed thresholds.
For this reason, the conventional technology uses the center pad method in which pads are linearly aligned in centers of chips.
In the case of the center pad method, circuits for controlling memory cell arrays are concentrated at centers of chips so that wiring densities thereof become high; hence, it is very difficult to form wirings efficiently.
Various documents such as Patent Document 1 teach solutions to the aforementioned drawback, in which data input/output pads, power pads, and address pads are appropriately arranged in connection with wires so as to provide efficient wirings in semiconductor memory devices.                Patent Document 1: Japanese Unexamined Patent Application Publication No. H08-139287        
FIG. 13 shows a chip of a semiconductor memory device disclosed in Patent Document 1, in which four banks 01 to 04 are arranged in respective regions and in which multiple pads are arranged in such a way that data input/output pads (i.e. DQ pads) are collectively arranged in the left of the center area, while command pads and address pads are collectively arranged in the right of the center area.
Since the DQ pads are collectively arranged in proximity to the banks 01 and 02, it is necessary to use relatively long IO buses for inputting and outputting data with the other banks 03 and 04.
In the case of FIG. 13, IO buses have lengths substantially matching half or more of the long sides of the chip, wherein in consideration of buses connected with data amplifiers (DA), memory cells of the other banks 03 and 04 must be connected to DQ pads via relatively long lengths therebetween.
The aforementioned semiconductor device suffers from a problem in that access times of data deviate in connection with respective banks, wherein the access time for outputting data from certain bank via DQ pads with the longest distance therebetween is regarded as the performance of a product. This degrades high-speed access of a semiconductor memory device.